Accelerated Verification of Digital Devices Using VHDL

As digital designs become more complex and increasingly include a processor on the chip, verification – and in particular the generation of testbenches – is becoming a bottleneck. This paper presents two aspects for improving the verification of microprocessors; program-less verification, and methods for handling large differences in abstraction level between a reference model and the actual design. Program-less verification is a type of pseudo random verification where the notion of a software program executing on the microprocessor has been abandoned. This removes some restrictions on the pseudo random data and instruction streams, and avoids limitations and bugs in software tools such as assemblers. A high level of abstraction is important when creating reference models,ion is important when creating reference models, since it reduces the risk for introducing errors in the reference, as well as the effort for coding it. However, the testbenches must then be able to cope with behavioural dif ferences due to phenomena such as prefetching, speculative execution etc.